The characteristics of a motherboard depend on several variables, the footprint, the chipset, the type of processor socket and the I / O connectors. The motherboard is the printed circuit supporting most of the components and connectors necessary for the operation of a compatible PC. It is essentially made up of printed circuits and connection ports which ensure the connection of all the components and peripherals specific to a microcomputer (hard disks (HDD / SSD), random access memory (RAM Random access memory), microprocessor, daughter cards, etc.)
PCI Express, abbreviated PCI-E or PCIe, is a standard developed by Intel. It specifies a local serial bus (“PCI express bus”) and a connector that is used to connect expansion cards to a computer’s motherboard. It replaces all expansion slots on a PC, including PCI and AGP. Thanks to the PCIe bus two PCIe cardscan talk to each other without going through the processor. PCI Express is derived from the PCI (Peripheral Component Interconnect) standard and allows manufacturers to simply adapt their existing expansion cards (the hardware layer is to be modified only). Possibility of replacing traditional PCI but also AGP, a fast port for graphics cards. Unlike PCI which is connected to the southbridge of the motherboard, PCI Express is often available at both the northbridge and the southbridge.
PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s. Consequently, a 16-lane PCIe connector (×16) can support an aggregate throughput of up to 8 GB/s. PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 work, with the other being v1.1 or v1.0a. The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture. Intel‘s first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, and Gigabyte) as of 21 October 2007. AMD started supporting PCIe 2.0 with its AMD 700 chipset series and NVidia started with the MCP72. All of Intel’s prior chipsets, including the Intel P35 chipset, supported PCIe 1.1 or 1.0a.
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until Q2 2010. New features for the PCI Express 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG’s analysis found that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCI Express protocol stack. PCI Express 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the bandwidth overhead from 20% of PCI Express 2.0 to approximately 1.54% (= 2/130). A desirable balance of 0 and 1 bits in the data stream is achieved by XORing a known binary polynomial as a “scrambler” to the data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by applying the XOR a second time. Both the scrambling and descrambling steps are carried out in hardware. PCI Express 3.0’s 8 GT/s bit rate effectively delivers 985 MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0. On 18 November 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.
The ATX format is an evolution of the Baby-AT format, it is designed to improve ergonomics. The layout of the connectors on an ATX motherboard optimizes the connection of peripherals, the IDE connectors are located on the drive side, and the motherboard components are oriented in parallel, so as to optimize heat dissipation. Features ATX 305 mm x 244 mm AGP / PCI 6.
The micro-atx format is an evolution of the ATX format, it keeps the main advantages while offering a smaller format (244x244mm), therefore a reduced cost. The micro-atx format offers a AGP connector and 3 PCI connectors.